A Novel Security Assessment Method Based on Linear Regression for Logic Locking

被引：0

作者：

Tsai, I-Chun ^{[1
,2
]}

Zhong, Yi ^{[1
,2
]}

Liu, Fang-Ru ^{[1
,2
]}

Feng, Jianhua ^{[1
,2
,3
]}

机构：

[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China

[2] Peking Univ, Sch Software & Microelect, Beijing 100871, Peoples R China

[3] Beida Binhai Informat Res, Tianjin 300450, Peoples R China

来源：

2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2019年

基金：

中国国家自然科学基金;

关键词：

hardware security; logic locking; security assessment; multiple linear regression; key-inputs modeling;

D O I：

10.1109/edssc.2019.8754415

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a novel logic locking security assessment method based on linear regression, by means of modeling between the distribution probabilities of key-inputs and observable outputs. The algorithm reveals a weakness of the encrypted circuit since the assessment can revoke the key-inputs within several iterations. The experiment result shows that the proposed assessment can be applied to varies of encrypted combinational benchmark circuits, which exceeds 85% of correctness after revoking the encrypted key-inputs.

引用

页数：3

共 6 条

[1]

Mishra P., 2017, Hardware IP security and trust, DOI 10.1007/978-3-319-49025-0

[2] Fault Analysis-Based Logic Encryption [J].

Rajendran, Jeyavijayan ;

Zhang, Huan ;

Zhang, Chi ;

Rose, Garrett S. ;

Pino, Youngok ;

Sinanoglu, Ozgur ;

Karri, Ramesh .

IEEE TRANSACTIONS ON COMPUTERS, 2015, 64 (02) :410-424

[3]

Rajendran J, 2012, DES AUT TEST EUROPE, P953

[4]

Rajendran J, 2012, DES AUT CON, P83

[5]

Roy JA, 2008, DES AUT TEST EUROPE, P948

[6] On Improving the Security of Logic Locking [J].

Yasin, Muhammad ;

Rajendran, Jeyavijayan ;

Sinanoglu, Ozgur ;

Karri, Ramesh .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (09) :1411-1424

← 1 →