A binocular CMOS range image sensor with bit-serial block-parallel interface using cyclic pipelined ADC's

被引：14

作者：

Kato, T ^{[1
]}

Kawahito, S ^{[1
]}

Kobayashi, K ^{[1
]}

Sasaki, H ^{[1
]}

Eki, T ^{[1
]}

Hisanaga, T ^{[1
]}

机构：

[1] Yamatake Corp, Fujisawa, Kanagawa, Japan

来源：

2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIC.2002.1015102

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A binocular CMOS image sensor used with a pair of aligned-in-parallel optical systems for range imaging is implemented. Sixteen compact cyclic pipelined analog-to-digital converters are integrated per an image sensor. The dedicated processor starts 16 x 16 FFT when the first bit-serial block-parallel data is obtained. The image sensor produces a 16 x 16 range image from a pair of 256 x 256 images, together with the dedicated pipelined FFT processor, at the maximum pipeline performance.

引用

页码：270 / 271

页数：2

共 6 条

[1]

Brajovic V., 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), P256, DOI 10.1109/ISSCC.2001.912630

[2]

KAWAHITO S, 1997, COMPRESSED DIGITAL O, P184

[3]

KAWAHITO S, 2001, P ISCAS, V4, P738

[4] A PIPELINED 5-MSAMPLE/S 9-BIT ANALOG-TO-DIGITAL CONVERTER [J].

LEWIS, SH ;

GRAY, PR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (06) :954-961

[5]

MORIKAWA M, 1999, P IEEE INT S IND EL, V3, P1208

[6]

STEVANOVIC N, 2000, CMOS IMAGE SENSOR HI, P104

← 1 →