Copper Direct-Bonding Characterization and Its Interests for 3D Integration

被引：52

作者：

Gueguen, Pierric ^{[1
]}

Di Cioccio, Lea ^{[1
]}

Gergaud, Patrice ^{[1
]}

Rivoire, Maurice ^{[2
]}

Scevola, Daniel ^{[2
]}

Zussy, Marc ^{[1
]}

Charvet, Anne Marie ^{[1
]}

Bally, Laurent ^{[1
]}

Lafond, Dominique ^{[1
]}

Clavelier, Laurent ^{[1
]}

机构：

[1] CEA, LETI, MINATEC, F-38054 Grenoble, France

[2] STMicroelectronics, F-38920 Crolles, France

来源：

JOURNAL OF THE ELECTROCHEMICAL SOCIETY | 2009年 / 156卷 / 10期

关键词：

D O I：

10.1149/1.3187271

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Three-dimensional (3D) technology is the next step in the development of microelectronic devices. Vertical interconnection is one of the challenging issues. Metal bonding might be one of the possible techniques to address it. In this work, direct Cu/Cu bonding at room temperature, atmospheric pressure. and ambient air was investigated. At room temperature, a 2.8 J/m(2) bonding toughness was achieved. An electron energy loss spectroscopy spectrum pointed out the absence of copper oxide at the interface. Morphological evolutions vs postbonding annealing were presented with transmission electron microscopy and X-ray diffraction analyses. The ohmic behavior of the bonding was highlighted. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3187271] All rights reserved.

引用

页码：H772 / H776

页数：5

共 14 条

[1] Copper bonded layers analysis and effects of copper surface conditions on bonding quality for three-dimensional integration [J].

Chen, KN ;

Tan, CS ;

Fan, A ;

Reif, R .

JOURNAL OF ELECTRONIC MATERIALS, 2005, 34 (12) :1464-1467

[2]

DICIOCCIO L, 2008, IMAPS

[3]

ENQUIST P, 2007, RTI C P, V64, P4943

[4]

Gueguen P, 2008, IEEE INT INTERC TECH, P61

[5]

Huang Z, 2008, ELEC COMP C, P12

[6] New developments in electron energy loss spectroscopy [J].

Keast, V. J. ;

Bosman, M. .

MICROSCOPY RESEARCH AND TECHNIQUE, 2007, 70 (03) :211-219

[7]

Lable R, 2008, IEEE INT INTERC TECH, P19

[8] Enabling technologies for 3D chip stacking [J].

Leduc, Patrick ;

Di Cioccio, Lea ;

Charlet, Barbara ;

Rousseau, Maxime ;

Assous, Myriamn ;

Bouchu, David ;

Roule, Anne ;

Zussy, Marc ;

Gueguen, Pierric ;

Roman, Antonio ;

Rozeau, Olivier ;

Heitzmann, Michel ;

Nieto, Jean-Pierre ;

Vandroux, Laurent ;

Haumesser, Paul-Henri ;

Quenouillere, Remi ;

Toffoli, Alain ;

Sixt, Pierre ;

Maitrejean, Sylvain ;

Clavelier, Laurent ;

Sillon, Nicolas .

2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM, 2008, :76-78

[9]

Maitrejean S, 2001, MAT RES S C, P301

[10] BONDING OF SILICON-WAFERS FOR SILICON-ON-INSULATOR [J].

MASZARA, WP ;

GOETZ, G ;

CAVIGLIA, A ;

MCKITTERICK, JB .

JOURNAL OF APPLIED PHYSICS, 1988, 64 (10) :4943-4950

← 1 2 →