An Efficient FPGA Implementation for Real-Time and Low-Power UAV Object Detection

In this paper, an efficient real-time hardware accelerator based on Field Programmable Gate Array (FPGA) is proposed for unmanned aerial vehicle (UAV) object detection. We first analyze the iSmart3-SkyNet (a popular UAV object detection network), using the roofline model. Then, a series of optimization strategies are proposed for low power and real-time UAV object detection based on FPGA. Stackable shared PE and regulable loop count improve the computing roof and the utilization of computing resources. Channel augmentation is used to increase the memory bandwidth, and improve the computing efficiency for shallow layers. Regulable Loop Count reduces unnecessary computation, and pre-load workflow improves the overall parallelism of heterogeneous systems. The results show that our accelerator (SEUT) achieves 78.6 frames per second and 0.068J per image with 0.73 Intersection over Union for object detection. Source code will be available at https://github.com/aicer1/accob.