Analysis of RLC Interconnect Delay Considering Thermal Effect

被引：0

作者：

Dong, Gang ^{[1
]}

Leng, Peng ^{[1
]}

Yang, Yintang ^{[1
]}

Chai, Changchun ^{[1
]}

机构：

[1] Xidian Univ, Inst Microelect, Xian 710071, Peoples R China

来源：

2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on the equivalent Elmore delay model, a new delay model that takes inductance and thermal effect into consideration is presented in this paper. The proposed model with high efficiency has closed-form expression. Its solution exhibits high accuracy as compared to the other models. Simulation results show that the error in the propagation delay is less than 10% for RLC tree example.

引用

页码：2248 / 2251

页数：4

共 50 条

[21] RLC interconnect crosstalk waveform evaluation
Lorival, J. E.
Deschacht, D.
2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, : 544 - 547
[22] Optimum wire shaping of an RLC interconnect
El-Moursy, MA
Friedman, EG
PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3, 2003, : 1459 - 1464
[23] Accurate analysis of interconnect trees with distributed RLC model and moment matching
Li, XC
Mao, JF
Huang, HF
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2004, 52 (09) : 2199 - 2206
[24] Power analysis of VLSI interconnect with RLC tree models and model reduction
Shin, Youngsoo
Lee, Junghyup
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2006, 15 (03) : 399 - 408
[25] An efficient method for terminal reduction of interconnect circuits considering delay variations
Liu, P
Tan, SXD
Li, H
Qi, ZY
Kong, J
McGaughy, B
He, L
ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 821 - 826
[26] Efficient RLC macromodels for digital IC interconnect
Tutuianu, B
Lehther, D
Pandey, M
Baldick, R
VLSI: SYSTEMS ON A CHIP, 2000, 34 : 293 - 304
[27] Optimum wire sizing of RLC interconnect with repeaters
El-Moursy, MA
Friedman, EG
INTEGRATION-THE VLSI JOURNAL, 2004, 38 (02) : 205 - 225
[28] Closed-form RC and RLC delay models considering input rise time
Kim, SoYoung
Wong, S. Simon
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (09) : 2001 - 2010
[29] Variational delay metrics for interconnect timing analysis
Agarwal, K
Sylvester, D
Blaauw, D
Liu, F
Nassif, S
Vrudhula, S
41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004, 2004, : 381 - 384
[30] Compact distributed RLC interconnect models - Part IV: Unified models for time delay, crosstalk, and repeater insertion
Venkatesan, R
Davis, JA
Meindl, JD
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (04) : 1094 - 1102

← 1 2 3 4 5 →