Strain Engineering for 3.5-nm Node in Stacked-Nanoplate FET

被引：12

作者：

Kim, Hyunsuk ^{[1
,2
]}

Son, Dokyun ^{[1
,2
]}

Myeong, Ilho ^{[1
,2
]}

Ryu, Donghyun ^{[1
,2
]}

Park, Jaeyeol ^{[1
,2
]}

Kang, Myounggon ^{[3
]}

Jeon, Jongwook ^{[4
]}

Shin, Hyungcheol ^{[1
,2
]}

机构：

[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 151742, South Korea

[2] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul 151742, South Korea

[3] Korea Natl Univ Transportat, Dept Elect Engn, Chungju 151742, South Korea

[4] Konkuk Univ, Dept Elect Engn, Seoul 05029, South Korea

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2019年 / 66卷 / 07期

关键词：

Monte Carlo (MC) simulation; self-heating effects (SHEs); stacked nanoplate FET; strain engineering; thermal resistance (R-th); SILICON-CARBON SOURCE/DRAIN; ENHANCEMENT;

D O I：

10.1109/TED.2019.2917503

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the overall performance of a stacked nanoplate FET was analyzed as a candidate for a 3.5-nm node. In order to conduct this analysis, Monte Carlo (MC) simulation was used to obtain near-realistic data and 3-D TCAD simulation data were fitted under the consideration of strain engineering. Through this process, the characteristics of the stacked nanoplate FET were analyzed in terms of structure optimization. In addition, strain effect, as one of the mechanical effects, to enhance the performance for nanoplate FET was simulated with the fitted data. This enhancement is predicted to deteriorate the performance by self-heating effects (SHEs). Therefore, the way in which ON-current (ION) increased by strain engineering influences SHEs was investigated, and appropriate strain engineering to obtain the best performance was proposed. Finally, the above analysis was confirmed using the Berkeley Short-channel IGFET Model Common Multi-Gate model.

引用

页码：2898 / 2903

页数：6

共 24 条

[1] Performance enhancement in uniaxial strained silicon-on-lnsulator N-MOSFETs featuring silicon-carbon source/drain regions [J].

Ang, Kah-Wee ;

Chui, King-Jien ;

Tung, Chih-Hang ;

Balasubramanian, Narayanan ;

Sarnudra, Ganesh S. ;

Yeo, Yee-Chia .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (11) :2910-2917

[2]

[Anonymous], 3 DIM DEV SIM 10 NM

[3]

[Anonymous], 2017, IEDM, DOI DOI 10.1109/IEDM.2017.8268429

[4]

[Anonymous], 2015, INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2.0

[5]

[Anonymous], 2016, PROC 2016 IEEE INT R

[6]

[Anonymous], BSIM CMG 109 0 0 MUL

[7]

[Anonymous], 2017, IEEE INT ELECT DEVIC

[8]

[Anonymous], 2018, UTBSOI MOSFET CORNER

[9]

Beppu Nobuyasu, 2012, PROPOSALS 2OMEGA MET

[10] Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors [J].

Cai, Linlin ;

Chen, Wangyong ;

Du, Gang ;

Zhang, Xing ;

Liu, Xiaoyan .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (06) :2647-2653

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