Clock-gating and its application to low power design of sequential circuits

This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques. It then uses the revering relationship between the triggering transition of the clock and the active cycles of various flip flops to generate a derived clock fur each flip flop in the circuit. A technique fur clerk gating is also presented, which generates a derived clock synchronous with the master clock. Design examples using gated clocks are provided nest. Experimental results show that these designs have ideal logic functionality with loser power dissipation compared to traditional designs.