Embedding a superscalar processor onto a chip multiprocessor

被引：3

作者：

Wu, CC ^{[1
]}

机构：

[1] Natl Changhua Univ Educ, Dept Comp Sci & Informat Engn, Changhua, Taiwan

来源：

MICROPROCESSORS AND MICROSYSTEMS | 2004年 / 28卷 / 04期

关键词：

chip multiprocessor; superscalar processor; multithreaded architecture; speculative execution; instruction-level parallelism;

D O I：

10.1016/j.micpro.2004.02.002

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Chip multiprocessors (CMPs) aim to develop both instruction-level and thread-level parallelisms to boost a system's performance. However, according to previous research results, CMPs outperform superscalar processors only in floating-point applications. Therefore, we have proposed a novel microprocessor, supporting two execution modes, to allow users to manually choose an appropriate mode to execute an application according to the workload characteristics. In the first mode, the processor acts like a conventional CMP. The second mode is derived from aggregating multiple processing elements in the CMP into a wide superscalar. Furthermore, we extend this innovative microarchitecture to support a third execution mode, whereby the processor keeps switching between the first and second modes when executing an application, according to the characteristics of subsequent instructions. As a result, this third mode can use both the advantages of a CMP and of a superscalar to execute an application. According to the performance analysis, Our processor can provide an optimum system performance for all benchmark programs, regardless of workload characteristics. Furthermore. our CMP outperforms a conventional CMP, exhibiting a speedup of up to 1.32. (C) 2004 Elsevier B.V. All rights reserved.

引用

页码：147 / 156

页数：10

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