Monolithic 3D neuromorphic computing system with hybrid CMOS and memristor-based synapses and neurons

被引:23
作者
An, Hongyu [1 ]
Ehsan, M. Amimul [2 ]
Zhou, Zhen [3 ]
Shen, Fangyang [4 ]
Yi, Yang [1 ]
机构
[1] Virginia Tech, Bradley Dept Elect & Comp Engn, Blacksburg, VA 24061 USA
[2] Univ Kansas, Dept Elect Engn & Comp Sci, Lawrence, KS 66045 USA
[3] Intel Corp, 3600 Juliette Ln, Santa Clara, CA 95054 USA
[4] New York City Coll Technol, Brooklyn, NY 11201 USA
关键词
Neurmorphic computing; Vertical REAM structure; Memristor; SPICE model; Monolithic 3D integration; Signal intensity encoding neuron; IMPEDANCE EXTRACTION; DESIGN; MODEL;
D O I
10.1016/j.vlsi.2017.10.009
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Because of fabrication compatibility to current semiconductor technology, three-dimensional integrated circuits (3D-ICs) offer promising near-term solutions for maintaining Moore's Law. 3D-ICs proffer high system speeds, massively parallel processing, low power consumption, and their high densities result in small footprints. In this paper, a novel 3D neuromorphic IC architecture which combines monolithic 3D integration and a synaptic array based on vertical resistive random-access memory structure (V-RRAM) is proposed. To analyze the electrical characteristics of the proposed synaptic array, a concise equivalent circuit model of the system is developed, and analytical calculations for each parameter of the equivalent circuit are provided. Moreover, a novel signal intensity encoding neuron design that can directly convert analog signal into a spiking waveform sequence is proposed and analyzed. A feasible 3D neuromorphic computing architecture is demonstrated. Applying the monolithic 3D integration technology on neuromorphic computing system hardware implementation can reduce the power consumption by 50%, and shrink die areas by 35%.
引用
收藏
页码:273 / 281
页数:9
相关论文
共 39 条
[1]   Lapicque's introduction of the integrate-and-fire model neuron (1907) [J].
Abbott, LF .
BRAIN RESEARCH BULLETIN, 1999, 50 (5-6) :303-304
[2]   True North: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip [J].
Akopyan, Filipp ;
Sawada, Jun ;
Cassidy, Andrew ;
Alvarez-Icaza, Rodrigo ;
Arthur, John ;
Merolla, Paul ;
Imam, Nabil ;
Nakamura, Yutaka ;
Datta, Pallab ;
Nam, Gi-Joon ;
Taba, Brian ;
Beakes, Michael ;
Brezzo, Bernard ;
Kuang, Jente B. ;
Manohar, Rajit ;
Risk, William P. ;
Jackson, Bryan ;
Modha, Dharmendra S. .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (10) :1537-1557
[3]  
[Anonymous], P DES C 2012
[4]  
[Anonymous], 2013, DESIGN AUTOMATION C
[5]  
[Anonymous], 3DIC
[6]   Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory [J].
Bai, Yue ;
Wu, Huaqiang ;
Wu, Riga ;
Zhang, Ye ;
Deng, Ning ;
Yu, Zhiping ;
Qian, He .
SCIENTIFIC REPORTS, 2014, 4
[7]   Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations [J].
Benjamin, Ben Varkey ;
Gao, Peiran ;
McQuinn, Emmett ;
Choudhary, Swadesh ;
Chandrasekaran, Anand R. ;
Bussat, Jean-Marie ;
Alvarez-Icaza, Rodrigo ;
Arthur, John V. ;
Merolla, Paul A. ;
Boahen, Kwabena .
PROCEEDINGS OF THE IEEE, 2014, 102 (05) :699-716
[8]   Point-to-point connectivity between neuromorphic chips using address events [J].
Boahen, KA .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2000, 47 (05) :416-434
[9]  
Clermidy F, 2014, ASIA S PACIF DES AUT, P563, DOI 10.1109/ASPDAC.2014.6742951
[10]   COLD FIBER POPULATION INNERVATING PALMAR AND DIGITAL SKIN OF MONKEY - RESPONSES TO COOLING PULSES [J].
DARIANSMITH, I ;
JOHNSON, KO ;
DYKES, R .
JOURNAL OF NEUROPHYSIOLOGY, 1973, 36 (02) :325-346