Inherently linear capacitor error-averaging techniques for pipelined A/D conversion

被引：32
作者：
Chiu, Y [1 ]
机构：
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 2000年 / 47卷 / 03期
关键词：
active capacitor error-averaging; average residue voltage; complementary residue pair; DNL; effective-number-of-bits; INL; passive capacitor error-averaging; pipelined A/D conversion; SNDR;
D O I：
10.1109/82.826750
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
New passive capacitor mismatch error-averaging techniques for pipelined analog-to-digital conversion is presented. The excellent linearity inherent to the architecture effectively eliminates the capacitor matching requirement that prevents a conventional monolithic pipelined analog-to-digital converter from reaching a 10-bit and above integral nonlinearity (INL) without trimming and/or calibration. Simulation results confirm the observation and a case of 14-bit INL realized by 7-bit capacitor matching is shown. The relaxed matching requirement enables the scale-down of the capacitor sizes to that of the KT/C limit. As a result, great reductions in both power consumption and chip area can be achieved.
引用
收藏
页码：229 / 232
页数：4
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