An emulated digital CNN implementation

被引：26

作者：

Keresztes, P

Zarándy, A

Roska, T

Szolgay, P

Bezák, T

Hidvégi, T

Jónás, P

Katona, A

机构：

[1] Istvan Szechenyi Polytech, H-9026 Gyor, Hungary

[2] Hungarian Acad Sci, Inst Comp & Automat, Analog & Neural Comp Syst Lab, H-1502 Budapest, Hungary

来源：

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 1999年 / 23卷 / 2-3期

关键词：

Cellular Neural Network; Arithmetic Unit; Processor Unit; State Transition Graph; Analog VLSI;

D O I：

10.1023/A:1008141017714

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new emulated digital CNN Universal Machine chip architecture is introduced and the main steps of the design process are shown in this paper. One core processor can be implemented on 2 x 2 mm(2) silicon area with a 0.35 mu m CMOS technology. Assuming an array of 24 processors on a chip, its speed is lns/virtual cell/CNN iteration with 12 bit precision. This enables the execution of over five hundred 3 x 3 convolution operations on each frame of a 240 x 320-pixel 25 fps digital image flow. Another new feature of the design is its variable precision capability. This allows the user to trade off precision for speed. The architecture supports some non-linear filter implementation as well.

引用

页码：291 / 303

页数：13

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