A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology

被引：21

作者：

Seo, Young-Suk ^{[1
]}

Lee, Jang-Woo ^{[1
]}

Kim, Hong-Jung ^{[1
]}

Yoo, Changsik ^{[1
]}

Lee, Jae-Jin ^{[2
]}

Jeong, Chun-Seok ^{[2
]}

机构：

[1] Hanyang Univ, Dept Elect & Comp Engn, Integrated Circuits Lab, Seoul 133791, South Korea

[2] Hynix Semicond, Ichon 467701, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2009年 / 56卷 / 01期

关键词：

Clock and data recovery (CDR); CMOS; subrate linear phase detector (PD);

D O I：

10.1109/TCSII.2008.2008520

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-mu m CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes much easier, and the maximum data rate is no longer limited by the speed of phase detection. The CDR shows 6.8-ps rms and 57.4-ps peak-to-peak jitter in the recovered clock and 10(-12) bit error rate for 2(31) - 1 pseudorandom binary-sequence input while consuming 144 mW from a 1.8-V supply.

引用

页码：6 / 10

页数：5

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