Area-Efficient FFT Kernel with Improved Use of GI for Multistandard MIMO-OFDM Applications

被引:2
作者
Tang, Song-Nien [1 ]
Chen, Yuan-Ho [2 ,3 ]
机构
[1] Chung Yuan Christian Univ, Informat & Comp Engn Dept, Taoyuan 32023, Taiwan
[2] Chang Gung Univ, Dept Elect Engn, Taoyuan 33302, Taiwan
[3] Chang Gung Univ, Inst Radiol Res, Chang Gung Mem Hosp, Taoyuan 33302, Taiwan
来源
APPLIED SCIENCES-BASEL | 2019年 / 9卷 / 14期
关键词
fast Fourier transform; FFT; kernel; MIMO; OFDM; multistandard; MDC FFT/IFFT PROCESSOR; VARIABLE-LENGTH; LOW-POWER; DESIGN; PERFORMANCE; ACCESS;
D O I
10.3390/app9142877
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
This study presents a fast Fourier transform (FFT) kernel for multistandard applications, which employ multiple-input, multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM). The proposed design uses a mixed-radix, mixed-multipath delay-feedback ((MRMDF)-D-2) structure, which enables 4/5/6-stream 64/128-point FFT. This approach allows the effective usage of guard intervals (GI) in conjunction with a novel resource-sharing scheme to improve area efficiency. An area-reduced constant multiplication unit and sorting buffer with minimal memory size further reduced an area overhead. A test chip was designed using UMC 90-nm technology, and was evaluated through post-layout simulation. The proposed design outperformed previous works in terms of the throughput per area.
引用
收藏
页数:15
相关论文
共 33 条
  • [1] A multi-mode IFFT/FFT processor for IEEE 802.11ac: design and implementation
    Ali, Abdelmohsen
    Hamouda, Walaa
    [J]. WIRELESS COMMUNICATIONS & MOBILE COMPUTING, 2016, 16 (13) : 1713 - 1725
  • [2] A low-power, high-performance, 1024-point FFT processor
    Baas, BM
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (03) : 380 - 387
  • [3] An Energy-Efficient Partial FFT Processor for the OFDMA Communication System
    Chen, Chao-Ming
    Hung, Chien-Chang
    Huang, Yuan-Hao
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57 (02) : 136 - 140
  • [4] Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
    Chen, Sau-Gee
    Huang, Shen-Jui
    Garrido, Mario
    Jou, Shyh-Jye
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (10) : 2869 - 2877
  • [5] A 2.4-Gsample/s DVFS FFT processor for MIMO OFDM communication systems
    Chen, Yuan
    Lin, Yu-Wei
    Tsao, Yu-Chi
    Lee, Chen-Yi
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (05) : 1260 - 1273
  • [6] Dahlman E., 2016, 4G LTE-Advanced Pro and the Road to 5G
  • [7] An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n
    Fu, Bo
    Ampadu, Paul
    [J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2009, 56 (01): : 59 - 68
  • [8] Designing pipeline FFT processor for OFDM (de)modulation
    He, SS
    Torkelson, M
    [J]. 1998 URSI SYMPOSIUM ON SIGNALS, SYSTEMS, AND ELECTR ONICS, 1998, : 257 - 262
  • [9] Hung CL, 2009, IEEE INT SYMP CIRC S, P705, DOI 10.1109/ISCAS.2009.5117846
  • [10] Hwang Y.T., 2007, P IEEE C COMP VIS PA, P1