Energy Evaluation for Two-level On-chip Cache with Non-Volatile Memory on Mobile Processors

被引：0

作者：

Matsuno, Shota ^{[1
]}

Tawada, Masashi ^{[1
]}

Yanagisawa, Masao ^{[1
]}

Kimura, Shinji ^{[1
]}

Togawa, Nozomu ^{[1
]}

Sugibayashi, Tadahiko ^{[2
]}

机构：

[1] Waseda Univ, Tokyo, Japan

[2] NEC Corp Ltd, Tokyo, Japan

来源：

2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2013年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As leakage power of traditional SRAM becomes larger, a ratio of static energy in total energy of memory architecture becomes also larger. Non-volatile memory (NVM) has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but consumes too much write energy. In this paper, we evaluate energy consumption of two-level cache using NVM in part on mobile processors and confirm that it effectively reduces energy consumption.

引用

页数：4

共 8 条

[1] [Anonymous], CACTI 6 0 TOOL MODEL
[2] SimpleScalar: An infrastructure for computer system modeling
Austin, T
Larson, E
Ernst, D
[J]. COMPUTER, 2002, 35 (02) : 59 - +
[3] Gerosa Gianfranco, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, P256, DOI 10.1109/ISSCC.2008.4523154
[4] Finding optimal L1 cache configuration for embedded systems
Janapsatya, Andhi
Ignjatovic, Aleksandar
Parameswaran, Sri
[J]. ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 796 - 801
[5] MediaBench: A tool for evaluating and synthesizing multimedia and communications systems
Lee, CH
Potkonjak, M
Mangione-Smith, WH
[J]. THIRTIETH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, 1997, : 330 - 335
[6] Matsuno S., 2013, P 28 INT TECHN C CIR, P250
[7] Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache
Sun, Hongbin
Liu, Chuanyin
Xu, Wei
Zhao, Jizhong
Zheng, Nanning
Zhang, Tong
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (01) : 19 - 28
[8] Tawada M., 2011, P VLSI DES AUT TEST, P1

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