Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

被引：13

作者：

Amerasekera, A ^{[1
]}

Chang, MC ^{[1
]}

Duvvury, C ^{[1
]}

Ramaswamy, S ^{[1
]}

机构：

[1] UNIV ILLINOIS,COMP SIMULAT LAB,URBANA,IL 61801

来源：

IEEE CIRCUITS & DEVICES | 1997年 / 13卷 / 02期

关键词：

D O I：

10.1109/101.583606

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

[No abstract available]

引用

页码：7 / 10

页数：4

共 9 条

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[3]

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[8]

SUN E, 1978, TECH DIG IEDM, P478

[9] NUMERICAL-MODEL OF AVALANCHE BREAKDOWN IN MOSFETS [J].

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YAMAGUCHI, K ;

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