Architectures for finite Radon transform

被引：3

作者：

Rahman, CA ^{[1
]}

Badawy, W ^{[1
]}

机构：

[1] Univ Calgary, Dept Elect & Comp Engn, Calgary, AB T2N 1N4, Canada

来源：

ELECTRONICS LETTERS | 2004年 / 40卷 / 15期

关键词：

D O I：

10.1049/el:20040566

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7 x 7 size image blocks and are prototyped for processing CIF image sequence. The simulation and synthesis results show that the core speeds of the two proposed architectures are around 100 and 82 MHz. respectively.

引用

页码：931 / 932

页数：2