Remembrance of circuits past: Macromodeling by data mining in large analog design spaces

The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 10(3) to 10(5) fully simulated circuit solution candidates. What might we do, with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parameterized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental results show that we can automatically build useful nonlinear regression models for large analog design spaces.