Low-Temperature 3D Chip-Stacking Using Compliant Bump

被引：1

作者：

Watanabe, Naoya ^{[1
]}

Mori, Takamichi ^{[1
]}

Asano, Tanemasa ^{[1
]}

机构：

[1] Kyushu Univ, Grad Sch Informat Sci & Elect Engn, Nishi Ku, Fukuoka 8190395, Japan

来源：

EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3 | 2008年

关键词：

D O I：

10.1109/EPTC.2008.4763466

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11 mu m / 20 mu m, chip-stacking temperature: 30 degrees C) using the compliant bump. Low-temperature 3D chip-stacking was carried Out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.

引用

页码：393 / 398

页数：6

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