Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures

被引：27
作者：
Liu, Xi [1 ]
Wu, Meile [1 ]
Jin, Xiaoshi [1 ]
Chuai, Rongyan [1 ]
Lee, Jong-Ho [2 ,3 ]
机构：
[1] Shenyang Univ Technol, Sch Informat Sci & Engn, Shenyang 110870, Peoples R China
[2] Seoul Natl Univ, Sch EECS Engn, Seoul 151742, South Korea
[3] Seoul Natl Univ, ISRC, Seoul 151742, South Korea
来源：
JOURNAL OF COMPUTATIONAL ELECTRONICS | 2014年 / 13卷 / 02期
基金：
中国国家自然科学基金;
关键词：
Junctionless (JL); FinFETs; Triple-gate (TG); Double-gate (DG); Device simulation; CURRENT MODEL; NANOWIRE TRANSISTORS; MOSFETS;
D O I：
10.1007/s10825-014-0562-3
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, both the forward and reverse characteristics of junctionless (JL) FinFETs with deep nanoscale design parameters have been studied through TCAD device simulation by considering band-to-band tunneling. Design optimization of the JL TG FinFETs has been performed by investigating the influence of the variations of design parameters such as body doping, channel length, body thickness, fin height and gate oxide thickness. The performance difference between the DG and TG JL FinFETs also has been compared by considering the structure difference. The scheme of device optimization has been proposed.
引用
收藏
页码：509 / 514
页数：6
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