Test-Access Solutions for Three-Dimensional SOCs

被引：0
|
作者：
Wu, Xiaoxia [1 ]
Chen, Yibo [1 ]
Chakrabarty, Krishnendu [2 ]
Xie, Yuan [1 ]
机构：
[1] Penn State Univ, Dept Comp Sci & Engn, University Pk, PA 16802 USA
[2] Duke Univ, Dept Elect & Comp Engn, Durham, NC 27708 USA
来源：
2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS | 2008年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present a design technique for providing test access to 3D core-based SOCs under constraints on the number of TSVs and the TAM bitwidth. The associated optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs.
引用
收藏
页码：1040 / 1040
页数：1
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