Efficient equivalence checking with partitions and hierarchical cut-points

被引：2

作者：

Anastasakis, D ^{[1
]}

McIlwain, L ^{[1
]}

Pilarski, S ^{[1
]}

机构：

[1] Synopsys Inc, Hillsboro, OR 97124 USA

来源：

41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004 | 2004年

关键词：

design verification; logic design; verification; equivalence checking;

D O I：

10.1145/996566.996714

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Previous results show that both flat and hierarchical methodologies present obstacles to effectively completing combinational equivalence checking. A new approach that combines the benefits while effectively dealing with the pitfalls of both styles of equivalence checking is presented.

引用

页码：539 / 542

页数：4

共 6 条

[1]

Abramovici M, 1990, DIGITAL SYSTEMS TEST

[2]

Anastasakis D, 2002, DES AUT CON, P305, DOI 10.1109/DAC.2002.1012640

[3]

BRAND D, 1993, 1993 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, P534, DOI 10.1109/ICCAD.1993.580110

[4]

BRYANT RE, 1986, IEEE T CAD

[5] Robust latch mapping for combinational equivalence checking [J].

Burch, JR ;

Singhal, V .

1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, :563-569

[6] Tight integration of combinational verification methods [J].

Burch, JR ;

Singhal, V .

1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, :570-576

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