High-voltage UMOSFETs in 4H SiC

被引：29

作者：

Khan, IA ^{[1
]}

Cooper, JA ^{[1
]}

Capano, MA ^{[1
]}

Isaacs-Smith, T ^{[1
]}

Williams, JR ^{[1
]}

机构：

[1] Purdue Univ, Sch ECE, W Lafayette, IN 47907 USA

来源：

PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS | 2002年

关键词：

D O I：

10.1109/ISPSD.2002.1016195

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report the design and fabrication of UMOSFETs on 4H-SiC with specific on-resistances of 105.1 mOmega cm(2) at a current density of 100 A/cm(2) and blocking voltage of 5,050 V. These devices incorporate an extended self-aligned p-bottom implant to protect the gate oxide from high electric fields. A novel shadow implant mask was developed to shield the sidewalls from any unwanted p-bottom implant. These UMOSFETs are also the first to incorporate a post-oxidation anneal (POA) in nitric oxide (NO) to improve the inversion layer electron mobility[1-3]. A single zone JTE with peak blocking voltage of 7,500 V was implemented in the device design.

引用

页码：157 / 160

页数：4

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