Design of a Low Power, High Speed, Energy Efficient Full Adder Using Modified GDI and MVT Scheme in 45nm Technology

This paper proposes the design of a low power, high speed, energy efficient full adder using modified Gate Diffusion Input (GDI) and Mixed Threshold Voltage (MVT) scheme in 45nm technology. The proposed design on comparison with the traditional full adder composed of CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), respectively, exhibited a considerable amount of reduction in terms of average power consumption (P-avg), peak power consumption (P-peak), delay time, power delay product (PDP), energy delay product (EDP) as well as transistor count and hence surface area. P-avg is as low as 7.61x10(-7) watt while P-peak is as low as 6.21x10(-5) watt, delay time is found to be 2.05nano second while PDP is computed to be as low as 1.56x10(-15) Joule and EDP is evaluated to be as low as 3.20x10(-24) Js for 0.9 volt power supply. The simulation of the proposed design has been performed in HSPICE and the layout has been designed in Microwind.