Low-voltage and High-speed Flipped Voltage Follower Using DTMOS transistor

被引:0
作者
Niranjan, Vandana [1 ]
Kumar, Ashwani [1 ]
Jain, Shail Bala [1 ]
机构
[1] Indira Gandhi Delhi Tech Univ Women, Dept Elect & Commun Engn, New Delhi, India
来源
2014 INTERNATIONAL CONFERENCE ON SIGNAL PROPAGATION AND COMPUTER TECHNOLOGY (ICSPCT 2014) | 2014年
关键词
Flipped voltage follower; DTMOS; low voltage analog signal processing; Triple well CMOS process; low power; DISTORTION; CMOS;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In the past body terminal was considered as an exclusive source of unwanted second order effects. But recently use of body terminal is becoming an attractive opportunity for improving the performance of analog integrated circuits. Low frequency harmonic distortion stems from the body effect and is dependent on body effect coefficient. In most of the analysis, body effect present in conventional flipped voltage follower (FVF) has been neglected however in submicron low voltage circuits it cannot be neglected. In this paper, we propose to utilize body effect positively using dynamic threshold MOS (DTMOS) transistor. The proposed FVF exhibits linear behaviour for large excursions of the output voltage and linear range has increased by +/- 20 mV. There is an improvement in the slew-rate(SR) performance and SR has become more symmetrical in proposed FVF. The proposed FVF is mapped on to the TSMC 250nm CMOS technology. Simulations at low supply voltage of 1.3V validate the proposed FVF. The proposed FVF is expected to be useful in low voltage high speed analog signal processing applications.
引用
收藏
页码:145 / 150
页数:6
相关论文
共 15 条
[1]   Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI [J].
Assaderaghi, F ;
Sinitsky, D ;
Parke, SA ;
Bokor, J ;
Ko, PK ;
Hu, CM .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (03) :414-422
[2]   Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower [J].
Blakiewicz, G. .
IET CIRCUITS DEVICES & SYSTEMS, 2011, 5 (05) :418-423
[3]   The flipped voltage follower:: A useful cell for low-voltage low-power circuit design [J].
Carvajal, RG ;
Ramírez-Angulo, J ;
López-Martín, A ;
Torralba, A ;
Galán, JAG ;
Carlosena, A ;
Chavero, FM .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (07) :1276-1291
[4]   Reliable circuit techniques for low-voltage analog design in deep submicron standard CMOS: A tutorial [J].
Fayomi, CJB ;
Sawan, M ;
Roberts, GW .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2004, 39 (01) :21-38
[5]   Bulk-Driven Flipped Voltage Follower [J].
Haga, Yasutaka ;
Kale, Izzet .
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, :2717-2720
[6]   Highly linear voltage follower based on local feedback and cascode transistor with dynamic biasing [J].
Lujan, C. I. ;
Torralba, A. ;
Carvajal, R. G. ;
Ramirez-Angulo, J. .
ELECTRONICS LETTERS, 2011, 47 (04) :244-+
[7]  
Niranjan V., 2013, P 2013 IEEE INT C SI
[8]  
Niranjan V, 2011, J ACT PASSIV ELECTRO, V6, P89
[9]  
Rajput S. S., 2002, IEEE Circuits and Systems Magazine, V2, P24, DOI 10.1109/MCAS.2002.999703
[10]   Simple class-AB voltage follower with slew rate and bandwidth enhancement and no extra static power or supply requirements [J].
Ramirez-Angulo, J. ;
Lopez-Martin, A. J. ;
Carvajal, R. G. ;
Torralba, A. ;
Jimenez, M. .
ELECTRONICS LETTERS, 2006, 42 (14) :784-785