Low Power 16-T CMOS Full Adder Design

被引：0
作者：
Borude, Pravin V. [1 ]
Agrawal, Sushma S. [1 ]
机构：
[1] Govt Engn Coll, Dept Elect & Telecommun Engn, Aurangabad, Maharashtra, India
来源：
PROCEEDINGS OF THE 2018 SECOND INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL SYSTEMS (ICICCS) | 2018年
关键词：
Full Adder; 4-bit Adder; Multiplier; ADS; Cadence;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents 16-T Full Adder Design in 0.13 um CMOS Process. The CMOS topology have ultimate zero static loss. The purpose of the introduced design is to reduce the cheap area by using less number of transistors and optimization of power as compare to conventional transistor. The conventional method has 28 Transistor whereas the proposed Design has 16 transistor. Which makes demotion in utilization of power. Simulations show a marked power reduction over conventional 28-T Hybrid and 28-T Static designs in same technology. The conventional adder dissipate 420 mu W whereas the 16-T dissipate 284 mu W. The circuit is simulated in Advanced Design System and laid out in Cadence Layout XL for comparison of layout size. The cheap area 8308 mu m(2).
引用
收藏
页码：1130 / 1134
页数：5
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