Reconfigurable hardware implementation of Montgomery modular multiplication and parallel binary exponentiation

被引：19

作者：

Nedjah, N ^{[1
]}

Mourelle, LD ^{[1
]}

机构：

[1] State Univ Rio De Janeiro, Fac Engn, Dept Syst Engn & Computat, Rio De Janeiro, Brazil

来源：

EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS: ARCHITECTURES, METHODS AND TOOLS | 2002年

关键词：

D O I：

10.1109/DSD.2002.1115373

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Modular exponentiation and modular multiplication are the cornerstone computations performed in public-key cryptography systems such as RSA cryptosystem. The operations are time consuming for large operands. Much research effort is directed towards an efficient hardware implementation of both operations. This paper describes the characteristics of two architectures: the first one implements modular multiplication using a systolic version of the fast Montgomery algorithm and the other to implement the parallel binary exponentiation algorithm. The latter uses two Montgomery modular multipliers. Results in terms of space and time requirements for an FPGA prototype are given.

引用

页码：226 / 233

页数：8

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