A multigigahertz multimodulus frequency divider in 90-nm CMOS

被引:14
作者
Ali, Moustafa [1 ]
Hegazi, Emad [1 ]
机构
[1] Ain Shams Univ, Elect & Commun Engn Dept, Cairo 11371, Egypt
关键词
CML; frequency divider; low power; multimodulus; 90-nm bulk CMOS;
D O I
10.1109/TCSII.2006.885069
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief presents a multimodulus frequency divider with division ratio between 64 and 127 fabricated in 90-nm CMOS. By using a load-switching technique, high operating frequency, and low power static divider was achieved. The divider consists of six 2/3 divider stages. The maximum operating frequency is 4.7 GHz with current consumption 2.3 mA at low voltage supply 1.2 V and rms cycle-to-cycle jitter lower than 1 ps.
引用
收藏
页码:1333 / 1337
页数:5
相关论文
共 9 条
[1]   Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction [J].
Boon, CC ;
Do, MA ;
Yeo, KS ;
Ma, JG .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (06) :1042-1048
[2]   A BiCMOS upconverter with 1.9 GHz multiband frequency synthesizer for DVB-RCT application [J].
de Foucauld, E ;
Billiot, G ;
Mounet, C .
PROCEEDINGS OF THE 2005 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2005, :244-247
[3]  
DO MA, 2003, ELECT LETT, V39
[4]  
MAZOUFFRE O, 2003, SILICON MONOLITHIC I, P84
[5]   A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider [J].
Pellerano, S ;
Levantino, S ;
Samori, C ;
Lacaita, AL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (02) :378-383
[6]  
PERROT MH, 1997, THESIS MIT CAMBRIDGE, P95
[7]  
TSENG SC, 2005, P APMC, V2, P4
[8]   A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology [J].
Vaucher, CS ;
Ferencic, I ;
Locher, M ;
Sedvallson, S ;
Voegeli, U ;
Wang, ZH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (07) :1039-1045
[9]   Design of a low power wide-band high resolution programmable frequency divider [J].
Yu, XP ;
Do, MA ;
Jia, L ;
Ma, JG ;
Yeo, KS .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (09) :1098-1103