Performance analysis of buffering schemes in wormhole routers

被引:30
作者
Boura, YM [1 ]
Das, CR [1 ]
机构
[1] PENN STATE UNIV,DEPT COMP SCI & ENGN,UNIVERSITY PK,PA 16802
基金
美国国家科学基金会;
关键词
multistage interconnection networks; n-dimensional meshes; router design; virtual channels; wormhole switching;
D O I
10.1109/12.600826
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Wormhole switched input-buffered and middle-buffered routers with virtual channels are analyzed in this paper. Middle buffering refers to the placement of virtual channels between the demultiplexors and multiplexors of a crossbar switch. An analytical model for multistage interconnection networks using middle-buffered switches is developed. In addition, extensive simulation is conducted to assess the performance of the two buffering techniques in different network topologies. The study demonstrates that middle buffering with virtual channels provides better performance than input buffering with virtual channels in multistage interconnection networks, two-dimensional meshes, and hypercubes.
引用
收藏
页码:687 / 694
页数:8
相关论文
共 18 条
[2]  
ALVERSON R, 1990, JUN INT C SUP, P1
[3]  
[Anonymous], 1977, P 4 ANN S COMPUTER A
[4]  
[Anonymous], IEEE T COMPUTERS
[5]  
AOYAMA K, 1993, THESIS U ILLINOIS DE
[6]  
BORKAR S, 1990, 17TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, P70, DOI 10.1109/ISCA.1990.134510
[7]  
BOURA YM, 1995, THESIS PENNSYLVANIA
[8]  
DALLY WJ, 1987, IEEE T COMPUT, V36, P547, DOI 10.1109/TC.1987.1676939
[9]   VIRTUAL-CHANNEL FLOW-CONTROL [J].
DALLY, WJ .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 1992, 3 (02) :194-205
[10]  
*INT CORP, 1990, TOUCHST DELTA SYST D