III-V Integration on Si(100): Vertical Nanospades

被引:27
作者
Gueniat, Lucas [1 ]
Marti-Sanchez, Sara [2 ,3 ]
Garcia, Oscar [4 ]
Boscardin, Megane [1 ]
Vindice, David [1 ]
Tappy, Nicolas [1 ]
Friedl, Martin [1 ]
Kim, Wonjong [1 ]
Zamani, Mahdi [1 ]
Francaviglia, Luca [1 ]
Balgarkashi, Akshay [1 ]
Leran, Jean-Baptiste [1 ]
Arbiol, Jordi [2 ,3 ,5 ]
Fontcuberta i Morral, Anna [6 ,7 ]
机构
[1] Ecole Polytech Fed Lausanne, Lab Mat Semicond, CH-1015 Lausanne, Switzerland
[2] CSIC, Catalan Inst Nanosci & Nanotechnol ICN2, Campus UAB, Barcelona 08193, Catalonia, Spain
[3] BIST, Campus UAB, Barcelona 08193, Catalonia, Spain
[4] UPC, Calle Jordi Girona 1-3, Barcelona 08034, Spain
[5] ICREA, Pg Lluis Co 23, Barcelona 08010, Catalonia, Spain
[6] Ecole Polytech Fed Lausanne, Inst Mat, Lab Semicond Mat, CH-1015 Lausanne, Switzerland
[7] Ecole Polytech Fed Lausanne, Inst Phys, CH-1015 Lausanne, Switzerland
基金
瑞士国家科学基金会;
关键词
nanospades; GaAs nanowires; nanowires; vertical growth; 100] growth; Si(100); SELF-LIMITING OXIDATION; SOLAR-CELLS; GAAS NANOWIRES; CONTACT-ANGLE; GROWTH; SILICON; MECHANISM; POLARITY; HETEROSTRUCTURES; FABRICATION;
D O I
10.1021/acsnano.9b01546
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
III-V integration on Si(100) is a challenge: controlled vertical vapor liquid solid nanowire growth on this platform has not been reported so far. Here we demonstrate an atypical GaAs vertical nanostructure on Si(100), coined nanospade, obtained by a nonconventional droplet catalyst pinning. The Ga droplet is positioned at the tip of an ultrathin Si pillar with a radial oxide envelope. The pinning at the Si/oxide interface allows the engineering of the contact angle beyond the Young-Dupre equation and the growth of vertical nanospades. Nanospades exhibit a virtually defect-free bicrystalline nature. Our growth model explains how a pentagonal twinning event at the initial stages of growth provokes the formation of the nanospade. The optical properties of the nanospades are consistent with the high crystal purity, making these structures viable for use in integration of optoelectronics on the Si(100) platform.
引用
收藏
页码:5833 / 5840
页数:8
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