A balanced capacitive threshold-logic gate

In this paper a new threshold gate is proposed. Its main characteristics are high fan-in (128-inputs), low delay time (8.35 ns), low power consumption (< 400 mu W) and optimal implementation of any threshold function. The gate can evaluate multiple input vectors in the same evaluation phase with only one clock signal. Synchronous (pipe-line) and asynchronous operations are possible, which makes it very suitable to implement logic designs with reduced depth. HSPICE simulations and simulation with files extracted from a layout in 0.6 mu m double-poly CMOS technology are presented, showing the validity of the proposed gate.