CLA based Floating-point adder suitable for chaotic generators on FPGA

Chaotic generators have been tremendously used In many applications over the past few years specially for encryption purposes. These generators are used to replicate the behavior of chaotic systems in real world applications. But they often suffer from lack of precision and low speeds. In this paper a floatingpoint adder is implemented based on the carry look ahead (CIA) architecture that is highly optimized in terms of speed and area making it specifically suited for use in chaotic generators. The proposed design is implemented on Virtex 5 FPGA with achieved frequency about 250 MHZ.