Performance Pathologies in Hardware Transactional Memory

被引:0
|
作者
Bobba, Jayaram [1 ]
Moore, Kevin E. [1 ]
Volos, Haris [1 ]
Yen, Luke [1 ]
Hill, Mark D. [1 ]
Swift, Michael M. [1 ]
Wood, David A. [1 ]
机构
[1] Univ Wisconsin, Dept Comp Sci, Madison, WI 53706 USA
来源
ISCA'07: 34TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, CONFERENCE PROCEEDINGS | 2007年
关键词
Transactional memory; hardware; performance; pathology; contention management;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously proposed HTMs represent three points in this design space: lazy conflict detection, lazy version management, committer wins (LL); eager conflict detection, lazy version management, requester wins (EL); and eager conflict detection, eager version management, and requester stalls with conservative deadlock avoidance (EE). To isolate the effects of these high-level design decisions, we develop a common framework that abstracts away differences in cache write policies, interconnects, and ISA to compare these three design points. Not surprisingly, the relative performance of these systems depends on the workload. Under light transactional loads they perform similarly, but under heavy loads they differ by up to 80%. None of the systems performs best on all of our benchmarks. We identify seven performance pathologies-interactions between workload and system that degrade performance-as the root cause of many performance differences: FRIENDLYFIRE, STARVINGWRITER, SERIALIZEDCOMMIT, FUTILESTALL, STARVINGELDER, RESTARTCONVOY, and DUELINGUPGRADES. We discuss when and on which systems these pathologies can occur and show that they actually manifest within TM workloads. The insight provided by these pathologies motivated four enhanced systems that often significantly reduce transactional memory overhead. Importantly, by avoiding transaction pathologies, each enhanced system performs well across our suite of benchmarks.
引用
收藏
页码:81 / 91
页数:11
相关论文
共 50 条
  • [21] Seer: Probabilistic Scheduling for Hardware Transactional Memory
    Diegues, Nuno
    Romano, Paolo
    Garbatov, Stoyan
    ACM TRANSACTIONS ON COMPUTER SYSTEMS, 2017, 35 (03):
  • [22] Transactional memory: The hardware-software interface
    McDonald, Austen
    Carlstrom, Brian D.
    Chung, JaeWoong
    Minh, Chi Cao
    Chafi, Hassan
    Kozyrakis, Christos
    Olukotun, Kunle
    IEEE MICRO, 2007, 27 (01) : 67 - 76
  • [23] Efficient Transaction Nesting in Hardware Transactional Memory
    Liu, Yi
    Su, Yangming
    Zhang, Cui
    Wu, Mingyu
    Zhang, Xin
    Li, He
    Qian, Depei
    ARCHITECTURE OF COMPUTING SYSTEMS - ARCS 2010, PROCEEDINGS, 2010, 5974 : 138 - +
  • [24] Conflict Graph Based Hardware Transactional Memory
    Zeng, Kun
    PROCEEDINGS OF 2010 3RD IEEE INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION TECHNOLOGY (ICCSIT 2010), VOL 5, 2010, : 496 - 501
  • [25] Core Reliability: Leveraging Hardware Transactional Memory
    Do, Sang Wook Stephen
    Dubois, Michel
    IEEE COMPUTER ARCHITECTURE LETTERS, 2018, 17 (02) : 105 - 108
  • [26] EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory
    Tomic, Sasa
    Akpinar, Ege
    Cristal, Adrian
    Unsal, Osman
    Valero, Mateo
    2013 INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE, 2013, 18 : 270 - 279
  • [27] Transactional Event Profiling in a Best-Effort Hardware Transactional Memory System
    Gaudet, Matthew
    Amaral, Jose Nelson
    PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT'12), 2012, : 475 - 475
  • [28] Mimosa: Protecting Private Keys Against Memory Disclosure Attacks Using Hardware Transactional Memory
    Li, Congwu
    Le Guan
    Lin, Jingqiang
    Luo, Bo
    Cai, Quanwei
    Jing, Jiwu
    Wang, Jing
    IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, 2021, 18 (03) : 1196 - 1213
  • [29] Performance Implications of Dynamic Memory Allocators on Transactional Memory Systems
    Baldassin, Alexandro
    Borin, Edson
    Araujo, Guido
    ACM SIGPLAN NOTICES, 2015, 50 (08) : 87 - 96
  • [30] On the interactions between ILP and TLP with hardware transactional memory
    Nicolas-Conesa, Victor
    Titos-Gil, Ruben
    Fernandez-Pascual, Ricardo
    Ros, Alberto
    Acacio, Manuel E.
    MICROPROCESSORS AND MICROSYSTEMS, 2024, 104