Static Pulsed Bus for on-chip interconnects

被引：15

作者：

Khellah, M ^{[1
]}

Tschanz, J ^{[1
]}

Ye, YB ^{[1
]}

Narendra, S ^{[1
]}

De, VV ^{[1
]}

机构：

[1] Intel Labs, Microprocessor Res, Hillsboro, OR USA

来源：

2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIC.2002.1015051

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Static Pulsed Bus (SPB) improves delay by 15%-25% or reduces energy by 12%-25% and peak current by 26%-34%, compared to the conventional static bus (SB) scheme, for 1500mum to 4500mum bus lengths in a 1000nm technology. Energy savings are maintained across all data activity factors.

引用

页码：78 / 79

页数：2