Systematic Approach for Trim Test Time Optimization: Case Study on a Multi-core RF SOC

It is well-known that complex sacs with RF and embedded power management (PM) modules require significant post manufacturing calibration to ensure that the device meets the design specifications. These calibrations are carried out by setting the register bits (which in turn help to finely adjust the parameters of the components inside the module containing these registers), a process commonly termed as trim. Not only must these calibrations precede any other manufacturing test operation, but they also require analog measurements and consume significant ATE resources and hence test time. As a result, it is commonly understood and observed that the calibration trim for such sacs with embedded RF and PM is often comparable to the sac test time itself This paper presents some crucial investigations into one such 45 nm multi-core RF sac designed at Texas Instruments. Its main contributions are: (i) The various trim operations are analyzed for the incurred test times and incurred ATE resources. (ii) Corresponding to each such operation, trim test time minimization techniques are proposed and experimental data on the accrued benefits is presented. (iii) A comprehensive hardware trim BIST controller is described, which enables trim automation and further optimization in complex sacs. Together, these investigations provide a recipe for efficiently performing trims in complex mixed-signal sacs with reduced test times and higher ATE enabled multi-site.