The Design of Sobel Edge Extraction System on FPGA

被引：0
|
作者：
Zheng, Yu [1 ]
机构：
[1] Beijing Univ Technol, Sch Software, Beijing 100124, Peoples R China
来源：
2017 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE AND TECHNOLOGY (IST 2017) | 2017年 / 11卷
关键词：
D O I：
10.1051/itmconf/20171108001
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Edge is a basic feature of an image, the purpose of edge detection is to reduce the amount of data in an image while preserving the shape information of objects. Field programmable gate arrays (FPGA) are best suited to implement image processing algorithms with the reason that it provides infinite reprogram ability and high parallelism. The aim of this paper is to design a real-time sobel extract system based on HLS method and the implement it on ZYNQ FPGA. The result shows the software processing time is almost 80 times than the hardware processing. The hardware acceleration has remarkable effect on sobel filtering.
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页数：6
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