Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers

被引:30
作者
Tu, Jin-Hao [1 ]
Van, Lan-Da [1 ]
机构
[1] Natl Chiao Tung Univ, Dept Comp Sci, Hsinchu 300, Taiwan
关键词
Baugh-Wooley algorithm; full-precision multiplier; fixed-width multiplier; pipeline; power efficient; reconfigurable; DESIGN;
D O I
10.1109/TC.2009.89
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a pipelined reconfigurable fixed-width Baugh-Wooley multiplier design framework that provides four configuration modes (CMs): n x n fixed-width multiplier, two n/2 x n/2 fixed-width multipliers, n/2 x n/2 full-precision multiplier, and two n/4 x n/4 full-precision multipliers. Furthermore, low-power schemes including gated clock and zero input techniques are employed to achieve the power-efficient pipelined reconfigurable design. The presented power-efficient pipelined reconfigurable fixed-width multiplier design not only generates a family of widely used multipliers but also leads to 10.59, 21.7, 28.84, and 31.58 percent power saving, on average, for n = 8, 16, 24, and 32, respectively, compared with that of the pipelined reconfigurable fixed-width multiplier without using the low-power schemes. On the other hand, compared with non-reconfigurable pipelined multiplier, we can save 0.81, 12.46, 17.93, and 23.2 percent power consumption, respectively, for n = 8, 16, 24, and 32.
引用
收藏
页码:1346 / 1355
页数:10
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