Design of a Low-Power and Low-Cost Booth-Shift/Add Multiplexer-based Multiplier

被引：0

作者：

Rashidi, Bahram ^{[1
]}

Sayedi, Sayed Masoud ^{[1
]}

Farashahi, Reza Rezaeian ^{[2
]}

机构：

[1] Isfahan Univ Technol, Dept Elect & Comp Engn, Esfahan 8415683111, Iran

[2] Isfahan Univ Technol, Dept Math, Esfahan, Iran

来源：

2014 22nd Iranian Conference on Electrical Engineering (ICEE) | 2014年

关键词：

low-power; low-cost; Multipexer-based; multipier; FPGA IMPLEMENTATION; PARALLEL MULTIPLIER; FULL-ADDERS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Design and implementation of a low-power and low-cost booth-shift/add multiplexer-based singed multiplier is presented. The main blocks of the circuit are constructed with some simple low-power structures. It includes multiplexer-based booth encoder and singed shifter blocks, multiplexer-based Manchester adder, an optimized and compact structure of control unit, and a low-power structure for full adder. The architecture has been successfully synthesized and verified using Xilinx ISE 11 and Spartan-3 FPGA. The results obtained by Xilinx Power Estimator (XPE) show that the proposed method has 58mW power consumption in 50MHz operation frequency.

引用

页码：14 / 19

页数：6

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