Adiabatic Logic Based Low Power Multiplexer and Demultiplexer

被引：0

作者：

Konwar, Shruti ^{[1
]}

Singha, Thockchom Birjit ^{[1
]}

Roy, Soumik ^{[1
]}

Vanlalchaka, Reginald H. ^{[2
]}

机构：

[1] Tezpur Univ, Dept Elect & Commun Engn, Tezpur 784002, Assam, India

[2] Mizoram Univ, Dept Elect & Commun Engn, Aizawl 796004, Mizoram, India

来源：

2014 INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND INFORMATICS (ICCCI) | 2014年

关键词：

Adiabatic logic; Multiplexer; Demutilplexer; PFAL; ECRL; 2n2n2p; power dissipation; power saving;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Minimizing power of digital circuits is always the first priority for VLSI designers. Following this trend, this paper presents a CMOS-based new design approach for a low power adiabatic 8:1 Multiplexer and 1:8 Demultiplexer. Some standard adiabatic logic styles like PFAL, ECRL, 2n2n2p are investigated, which are bettered by the proposed logic. The simulation is carried out in NI-Multisim software at 0.5 mu m CMOS technology for frequency range 200MHz - 800MHz.

引用

页数：5

共 9 条

[1]

[Anonymous], INT WORKSH POW TIM M

[2]

Kramer A., 1995, Proceedings. 1995 International Symposium on Low Power Design, P191, DOI 10.1145/224081.224115

[3] Pass-transistor adiabatic logic with NMOS pull-down configuration [J].

Liu, F ;

Lau, KT .

ELECTRONICS LETTERS, 1998, 34 (08) :739-741

[4] An efficient charge recovery logic circuit [J].

Moon, Y ;

Jeong, DK .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (04) :514-522

[5]

Singh Richa, 2013, INT J ADV ENG TECHNO, V6, P246

[6]

Singh Varun, 2013, INT J ENG RES APPL I, V3, P1582

[7]

Teichmann P, 2012, SPR SER ADV MICROELE, V34, P1, DOI 10.1007/978-94-007-2345-0

[8] Positive feedback in adiabatic logic [J].

Vetuli, A ;

Di Pascoli, S ;

Reyneri, LM .

ELECTRONICS LETTERS, 1996, 32 (20) :1867-1869

[9]

Vijayakumar S, 2010, MATH COMPUT SCI ENG, P83

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