Modeling of low-frequency noise in advanced CMOS devices

被引：8

作者：

Balestra, F. ^{[1
]}

Ghibaudo, G. ^{[1
]}

Jomaah, J. ^{[1
]}

机构：

[1] Univ Grenoble Alpes, IMEP LAHC, Grenoble INP Minatec, F-38016 Grenoble, France

来源：

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS | 2015年 / 28卷 / 06期

关键词：

low-frequency noise; modeling; characterization; variability; novel materials; advanced CMOS; MOS-TRANSISTORS; SOI MOSFETS; FLICKER NOISE; N-MOSFETS; GATE; VARIABILITY; INTERFACE; INVERSION; SIMULATION; MOBILITY;

D O I：

10.1002/jnm.2052

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The modeling and characterization of low-frequency noise and noise variability in various regimes of operation are investigated for the main advanced complementary metal-oxide semiconductor (CMOS) technologies. Novel materials and innovative device architectures from 0.5m to 20nm gate lengths are studied. The impact of gate stack, realized with ultrathin oxides, polysilicon gate and high-k/metal gate is analyzed. The influence of alternative channel materials, in particular ultrathin body silicon-on-insulator layers, strain Si and III-V materials is addressed. The comparison of low-frequency noise in advanced device architectures, including bulk Si, fully depleted SOI, FinFET, junctionless, and multi-gates structures, is shown. Accurate noise models, taking into account the main physical mechanisms, are proposed for all these very advanced technologies, which will be needed for the nanoelectronics of the next decade. Copyright (c) 2015 John Wiley & Sons, Ltd.

引用

页码：613 / 627

页数：15

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