CMOS Bulk-Controlled Fully Programmable Neuron for Artificial Neural Networks

In this paper, the design procedure of a novel neuron is discussed. Starting from the activation function circuit which is based on the modification of regulated cascode structure, a new scheme is presented which can produce the logistic function with high percentage of accuracy. The main advantage of the proposed function generator circuit is its full programmability feature in which its output waveform slope can easily be adjusted by means of the control voltages applied to the bulks of input stage metal oxide semiconductor (MOS) transistors. Also, the output waveform can easily be converted to a step function with the help of bias changes for the input transistors. Following the concepts of the previous work by the authors, the designed activation function has a good compatibility with the employed synapse. Low power and small active-area consumption are the other features of the proposed circuit which qualify it for hardware implementation of neural networks. Post-layout simulation results based on complementary metal-oxide-semiconductor (CMOS) 0.18 mu m twin-tub fabrication standard process depict the correct behaviour of the designed circuits and demonstrate 96% accuracy for the proposed activation function structure. The power dissipation of the activation function circuit is 72 mu W at the worst case for 1.8 power supply voltage.