An 8 Bit 4 GS/s 120 mW CMOS ADC

被引：113

作者：

Wei, Hegong ^{[1
]}

Zhang, Peng ^{[2
]}

Sahoo, Bibhu Datta ^{[3
]}

Razavi, Behzad ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

[2] Tsinghua Univ, Beijing 100036, Peoples R China

[3] Amrita Univ, Dept Elect & Commun Engn, Amritapuri, Kerala, India

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 08期

关键词：

Analog-to-digital conversion; interleaving; pipelined analog-to-digital converter (ADC); time error detection and correction; timing calibration; variable delay lines; CALIBRATION TECHNIQUE; BLIND CALIBRATION; TIMING-SKEW; MISMATCH;

D O I：

10.1109/JSSC.2014.2313571

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.

引用

页码：1751 / 1761

页数：11

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