Switch design and implementation for Network-on-Chip

When Network on Chip (NoC) is being developed in recent years, new challenges are accruing since a large number of heterogeneous cores are integrated on a single silicon die: On-chip switching networks seem to be one, scalable global interconnection solution for SoC. Packet switching is becoming predominant in today's NoC, the main advantage is that it supports many cores communicating simultaneously without dedicated data paths. Disadvantages are also obvious, packets may get lost in transmission since there are no predictable paths between cores. It takes extra time to reorder packets after they arrive at destination. Therefore, packet switching is not used for the multicast-supporting (MS) and guaranteed-throughput (GT) switching networks that require restricted latency and reliable data transmission. Time-space-time (TST) switch - designed for circuit switching networks using time division multiplexing (TDM) scheme is used in our MS & GT switching network. With this architecture, data can be efficiently transmitted in restricted channels and arrive after a constant latency. In the multimessage multicasting TST switch supporting messages with one sender and multiple receivers, each input buffer has only one read port, meaning that only one memory location can be accessed each clock cycle. To make the read/write operations parallel and hence reduce the demand on read/write bandwidth, scheduling is required. The switch employs an approximation algorithm for multimessage multicasting since scheduling of multicast communication is an NP-hard problem. With an approximation bound of qd + f(1/a) (d - 1) for fan-out f >= 3, the throughput increases when the data width grows. The main design objective is to develop a switch with very small area and delay, enabling its immediate practical use.