A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency

被引：22

作者：

Taft, Robert C. ^{[1
]}

Francese, Pier Andrea ^{[1
]}

Tursi, Maria Rosaria ^{[1
]}

Hidri, Ols ^{[1
]}

MacKenzie, Alan ^{[2
]}

Hoehn, Tobias ^{[1
]}

Schmitz, Philipp ^{[1
]}

Werker, Heinz ^{[1
]}

Glenny, Andrew ^{[3
]}

机构：

[1] Natl Semicond Corp, D-82008 Unterhaching, Germany

[2] Natl Semicond UK Ltd, Greenock PA16 OEQ, Scotland

[3] Natl Semicond Corp, Santa Clara, CA 95051 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 12期

关键词：

Analog-to-digital conversion; calibration; CMOS analog integrated circuits; folding; high-speed techniques; interpolation; pipelined; Nyquist converter; A-D CONVERTER; CMOS;

D O I：

10.1109/JSSC.2009.2032634

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simplifies their extension to higher resolution by building the converter out of identical but scaled pipelined cascaded folding stages. In this unified folding architecture the parallel coarse channel has been eliminated by recursively using the previous folding stage as the coarse channel for each following cascaded stage. This new architecture is demonstrated in a 10-bit ADC using six cascaded folding-by-3 stages with a total folding order of 729. At 1.0 GS/s, this inter-leave-by-2 ADC achieves < +/-0.2 LSB DNL, <= +/-0.5 LSB INL, 9.2 ENOB at 100 MHz input, 9.1 ENOB at Nyquist, and 8.8 ENOB at 1 GHz input. The value at F(IN) = 1 GHz is 1 ENOB higher than any value published to date. The power consumption from a single 1.8 V supply is 1.2 W/channel which includes the LVDS drivers for this dual-channel (I and Q each running at 1 GS/s) ADC.

引用

页码：3294 / 3304

页数：11

共 15 条

[1] FAST ADC [J].