Standard Cell Library and Automated Design Flow for Circuits on Flexible Substrates

A-Si:H TFTs are traditionally used in backplane arrays for active matrix displays and occasionally in row or column drive electronics with current efforts focusing on flexible displays and drivers. This paper extends flexible electronics to complex digital circuitry by designing a standard cell library for a-Si:H TFTs on flexible stainless steel and plastic substrates. The standard cell library enables layout automation with a standard cell place and route tool, significantly speeding the layout of a-Si:H digital circuits on the backplane to enhance display functionality. Since only n-channel transistors are available, the gates are designed with a bootstrap pull-up network to ensure good output voltage swings. The library developed consists of 7 gates: 5 combinational gates (Inverter, NAND2, NOR2, NOR3, and MUX2) and 2 sequential gates (latch and `D' flip-flop). Test structures have been fabricated to experimentally characterize the delay vs. fan-out of the standard cells. Automatic extraction of electrical interconnections from layout, enabling layout versus schematic (LVS) has also incorporated into the existing tool suite for bottom gate a-Si:H TFTs. A 3bit counter was designed, fabricated and tested to demonstrate the standard cell library is described.