Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP, and WS2-Based n-MOSFETs for Future Technology Nodes-Part I: Device-Level Comparison

被引:3
作者
Agarwal, Tarun Kumar [1 ]
Rau, Martin [1 ]
Radu, Iuliana [2 ]
Luisier, Mathieu [1 ]
Dehaene, Wim [3 ]
Heyns, Marc [2 ,4 ]
机构
[1] Swiss Fed Inst Technol, Dept Elect Engn, CH-8092 Zurich, Switzerland
[2] IMEC, CMOS Program, B-3001 Leuven, Belgium
[3] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Leuven, Belgium
[4] Katholieke Univ Leuven, B-3001 Leuven, Belgium
关键词
2-D materials; benchmarking; double-gate (DG) FET FinFET; InGaAs; monolayer black phosphorus (BP); monolayer WS2; nanowire (NW) FET; Si; ELECTRON-MOBILITY; BAND-STRUCTURE; TRANSPORT; GATE; GE;
D O I
10.1109/TED.2019.2912005
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To continue with the scaling of highperformance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III-V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes.
引用
收藏
页码:3608 / 3613
页数:6
相关论文
共 35 条
[1]  
AGARWAL T, 2017, IEDM, P54, DOI DOI 10.1109/IEDM.2017.8268336
[2]   Material-Device-Circuit Cooptimization of 2D Material based FETs for Ultra-Scaled Technology Nodes [J].
Agarwal, Tarun Kumar ;
Soree, Bart ;
Radu, Iuliana ;
Raghavan, Praveen ;
Iannaccone, Giuseppe ;
Fiori, Gianluca ;
Dehaene, Wim ;
Heyns, Marc .
SCIENTIFIC REPORTS, 2017, 7
[3]  
[Anonymous], IEDM
[4]   Electron effective mobility in strained-Si/Si1-xGex MOS devices using Monte Carlo simulation [J].
Aubry-Fortuna, V ;
Dollfus, P ;
Galdin-Retailleau, S .
SOLID-STATE ELECTRONICS, 2005, 49 (08) :1320-1329
[5]   A survey of ohmic contacts to III-V compound semiconductors [J].
Baca, AG ;
Ren, F ;
Zolper, JC ;
Briggs, RD ;
Pearton, SJ .
THIN SOLID FILMS, 1997, 308 :599-606
[6]   Strain-induced, off-diagonal, same-atom parameters in empirical tight-binding theory suitable for [110] uniaxial strain applied to a silicon parametrization [J].
Boykin, Timothy B. ;
Luisier, Mathieu ;
Salmani-Jelodar, Mehdi ;
Klimeck, Gerhard .
PHYSICAL REVIEW B, 2010, 81 (12)
[7]  
del Alamo JA, 2013, PROC EUR S-STATE DEV, P16, DOI 10.1109/ESSCIRC.2013.6649061
[8]   Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs [J].
Esseni, D ;
Abramo, A ;
Selmi, L ;
Sangiorgi, E .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (12) :2445-2455
[9]  
Ferry D. K., 2014, INT J HIGH SPEED ELE, V17, P384, DOI [10.1109/NANO.2006.247675, DOI 10.1109/NANO.2006.247675]
[10]   Simulation of electron transport in high-mobility MOSFETs: Density of states bottleneck and source starvation [J].
Fischetti, M. V. ;
Wang, L. ;
Yu, B. ;
Sachs, C. ;
Asbeck, P. M. ;
Taur, Y. ;
Rodwell, M. .
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :109-+