Design of power-controlled Class 1 Bluetooth CMOS power amplifier

In this paper, an RF power amplifier intended for Class 1 Bluetooth application is designed using 0.35 mu m CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35 mu m CMOS process using a transistor with total width of 901im and 18 fingers and it shows an excellent agreement with theft and S-parameter measurement data up to 6GHz. Effect of pads and bondwires are also taken into consideration during the design process of the PA. After postlayout simulations, the amplifier delivers an output power of 19dBm with 33.7 % PAE under 3.3V supply. This amplifier has a power control feature. Its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing.