Design and Analysis of an Adaptively Biased Low-Dropout Regulator Using Enhanced Current Mirror Buffer

This paper presents an adaptively biased low-dropout regulator using an enhanced current mirror (ECM) buffer for effectively driving the gate of the PMOS power transistor. The proposed ECM buffer offers very low output impedance, which pushes out the pole at the gate of the PMOS power transistor to improve the stability. At the same time, it offers a symmetric pull-up/down slew rate to enhance the speed of the buffer, whenever the regulator is under large signal operation during the load transient. Moreover, the ECM buffer is modified to develop the regulator topology without introducing an error amplifier as a separate independent stage. It helps to minimize the overall quiescent current consumption at low-load condition and makes frequency compensation easier. Finally, the speed of the adaptive bias loop is increased by avoiding the highly capacitive gate node of the PMOS power transistor. A comprehensive small-signal analysis of the proposed regulator is also carried out for a clear understanding of the stability of each loop considering the interaction of the other loop. The regulator is implemented in a 0.18-mu m CMOS technology with a quiescent current of 900 nA. A maximum transient output voltage variation of 2.1% is observed with C-o = 470 nF.