Analysis of Power Management Techniques in Multicore Processors

被引:3
作者
Nagalakshmi, K. [1 ]
Gomathi, N. [2 ]
机构
[1] Hindusthan Inst Technol, Dept Comp Sci & Engn, Coimbatore, Tamil Nadu, India
[2] Vel Tech Dr RR & Dr SR Univ, Dept Comp Sci & Engn, Madras, Tamil Nadu, India
来源
ARTIFICIAL INTELLIGENCE AND EVOLUTIONARY COMPUTATIONS IN ENGINEERING SYSTEMS, ICAIECES 2016 | 2017年 / 517卷
关键词
Multicore processor; Power management; DVFS; Clock gating; Task scheduling; Task migration; TASK; PERFORMANCE; ALGORITHM; SYSTEMS; SOFT;
D O I
10.1007/978-981-10-3174-8-35
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Power and performance have become significant metrics in the designing of multicore processors. Due to the ceasing of Moore's law and Dennard scaling, reducing power budget without compromising the overall performance is considered as a predominant limiting factor in multicore architecture. Of late technological advances in power management techniques of the multicore system substantially balance the conflicting goals of low power, low cost, small area, and high performance. This paper aims at ascertaining more competent power management techniques for managing power consumption of multicore processor through investigations. We highlight the necessity of the power management techniques and survey several new approaches to focus their pros and cons. This article is intended to serve the researchers and architects of multicore processors in accumulating ideas about the power management techniques and to incorporate it in near future for more effective fabrications.
引用
收藏
页码:397 / 418
页数:22
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