Design and FPGA-based Implementation of a High Performance 32-bit DSP Processor

被引：0

作者：

Ferdous, Tasnim ^{[1
]}

机构：

[1] Amer Int Univ Bangladesh, Dept Elect & Elect Engn, Dhaka, Bangladesh

来源：

2012 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY (ICCIT) | 2012年

关键词：

DSP processor; FPGA; Pipelined; Single cycle MAC; Hazard Handling;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

To meet the faster processing demand in consumer electronics, performance efficient DSP processor design is important. This paper presents a novel design and FPGA-based implementation of a 32 bit DSP processor to achieve high performance gain for reduced instruction set DSP processors. The proposed design includes a hazard-optimized pipelined architecture and a dedicated single cycle integer MAC to enhance the processing speed. Performance of the designed processor is evaluated against existing similar reduced instruction set DSP processor (MUN DSP-2000). Synthesis results and performance analysis of each system building component confirmed a significant performance improvement in the proposed DSP processor over the compared one.

引用

页码：484 / 489

页数：6

共 12 条

[1] Ahmed W., 2007, P DES AUT TEST EUR C, P319
[2] Anand K., 2007, THESIS
[3] [Anonymous], 2006, ALT PPC405A 32 BIT R
[4] Balpande M. R. S., 2011, P ICCSNT 11, P409
[5] Becker J., 2001, J SUPERCOMPUTING, V19
[6] CHOU CJ, P ICSPAT 93
[7] Cong J., 2011, ACM INT S NAN ARCH
[8] Ferdous T., 2012, INT J SCI ENG RES IJ, V3
[9] Ibrahim M. E. A., 2008, P ACSSC 08
[10] Karuri K., 2011, Application Analysis Tools for ASIP Design Application Profiling and Instruction-set Customization

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