A Flat Timing-Driven Placement Flow for Modern FPGAs

被引：13

作者：

Martin, Timothy ^{[1
]}

Maarouf, Dani ^{[1
]}

Abuowaimer, Ziad ^{[1
]}

Alhyari, Abeer ^{[1
]}

Grewal, Gary ^{[1
]}

Areibi, Shawki ^{[1
]}

机构：

[1] Univ Guelph, Guelph, ON, Canada

来源：

PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2019年

关键词：

Placement; FPGA; Timing Driven; UltraScale Architecture;

D O I：

10.1145/3316781.3317743

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

In this paper, we propose a novel, flat analytic timing-driven placer without explicit packing for Xilinx UltraScale FPGA devices. Our work uses novel methods to simultaneously optimize for timing, wirelength and congestion throughout the global and detailed placement stages. We evaluate the effectiveness of the flat placer on the ISPD 2016 benchmark suite for the xcvu095 UltraScale device, as well as on industrial benchmarks. Experimental results show that on average, FTPlace achieves an 8% increase in maximum clock rate, an 18% decrease in routed wirelength, and produces placements that require 80% less time to route when compared to Xilinx Vivado 2018.1.

引用

页数：6

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